摘要 :
Reviewed PLL basics and sources of noise in PLLs, Reviewed classical modeling techniques for PLLs, Introduced a new model approach based on pure Verilog-D, Compatible with digital verification flows, Non-linear noise folding effec...
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Reviewed PLL basics and sources of noise in PLLs, Reviewed classical modeling techniques for PLLs, Introduced a new model approach based on pure Verilog-D, Compatible with digital verification flows, Non-linear noise folding effect in Σ△ PLL is well predicted, Noise models were also included to provide a full picture of total performance, Modeling methodology can be extended to other analog/RF circuits.
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摘要 :
Reviewed PLL basics and sources of noise in PLLs, Reviewed classical modeling techniques for PLLs, Introduced a new model approach based on pure Verilog-D, Compatible with digital verification flows, Non-linear noise folding effec...
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Reviewed PLL basics and sources of noise in PLLs, Reviewed classical modeling techniques for PLLs, Introduced a new model approach based on pure Verilog-D, Compatible with digital verification flows, Non-linear noise folding effect in Σ△ PLL is well predicted, Noise models were also included to provide a full picture of total performance, Modeling methodology can be extended to other analog/RF circuits.
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摘要 :
FE Meshing Generate Volume FE Mesh Directly From CAD and Segmented Data with Simpleware Pores - What is the minimum size to include? Feasibility vs Accuracy - At 5 voxels across a sphere, we see ～2-4% error (internal study) - Any...
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FE Meshing Generate Volume FE Mesh Directly From CAD and Segmented Data with Simpleware Pores - What is the minimum size to include? Feasibility vs Accuracy - At 5 voxels across a sphere, we see ～2-4% error (internal study) - Any pore below 125voxels in size (5~3), are not included for the current study - Mesh Size = 8.5million elements - Mesh Time = 2.5hrs (Off the shelf PC - 64GB RAM, Intel 3.5GHz).
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摘要 :
LELE DPT is a likely RET at 22nm & below. Intelligent decomposition & coloring benefits product goals. Accurate, fast full chip coloring is difficult but possible. Design for DPT compliance essential for optimal density. DRC for DPT is useful but not a complete solution. DPT-aware OPC makes aggressive shrinks more manufacturable. DPT-aware verification is a requirement. Wafer process results show good promise overall....
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LELE DPT is a likely RET at 22nm & below. Intelligent decomposition & coloring benefits product goals. Accurate, fast full chip coloring is difficult but possible. Design for DPT compliance essential for optimal density. DRC for DPT is useful but not a complete solution. DPT-aware OPC makes aggressive shrinks more manufacturable. DPT-aware verification is a requirement. Wafer process results show good promise overall.
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摘要 :
This paper explains in details various overheads and tradeoffs in the power-gating designs. It also provides design considerations and guidelines for production power-gating design based on extensive power-gating design experience...
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This paper explains in details various overheads and tradeoffs in the power-gating designs. It also provides design considerations and guidelines for production power-gating design based on extensive power-gating design experience and in-depth understanding of the nature of the power-gating design. Special focuses are on physical power gating design and implementations including technology and Vt selections, power-gating strategies and design methods, switch power network synthesis, and wakeup rush current and charge-up latency control design techniques.
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摘要 :
1. Need for quantification of fit for purpose of Additive Manufactured parts 2. Need to quantify geometric and performance uncertainty 3. Demonstrated proof of concept workflow of using CT scanning technology, Image based Modeling...
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1. Need for quantification of fit for purpose of Additive Manufactured parts 2. Need to quantify geometric and performance uncertainty 3. Demonstrated proof of concept workflow of using CT scanning technology, Image based Modeling and Finite Element Simulation 4. Using image based meshing techniques, we demonstrated that bridging the gap from CT imaging to FE simulation while capturing the complexity of real-world geometries is feasible using standard computing power.
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摘要 :
1. Need for quantification of fit for purpose of Additive Manufactured parts 2. Need to quantify geometric and performance uncertainty 3. Demonstrated proof of concept workflow of using CT scanning technology, Image based Modeling...
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1. Need for quantification of fit for purpose of Additive Manufactured parts 2. Need to quantify geometric and performance uncertainty 3. Demonstrated proof of concept workflow of using CT scanning technology, Image based Modeling and Finite Element Simulation 4. Using image based meshing techniques, we demonstrated that bridging the gap from CT imaging to FE simulation while capturing the complexity of real-world geometries is feasible using standard computing power.
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摘要 :
The majority of today's designs contain significant analog and mixed-signal content. Even SoCs that are designed for essentially digital functions still require PLLs for timing control, digitally-controlled power management circui...
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The majority of today's designs contain significant analog and mixed-signal content. Even SoCs that are designed for essentially digital functions still require PLLs for timing control, digitally-controlled power management circuits, and high-speed interfaces. Obtaining high manufacturing yield of mixed-signal designs requires proper test architecture and planning upfront, the ability to automatically generate test vectors and the verification of the embedded test structures. This paper presents a design-for-test (DFT) methodology for getting test coverage in custom digital data paths used in the design of high speed interfaces.
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摘要 :
This paper presents the physical, statistical, and mathematical background necessary for properly translating between frequency-domain phase noise and various time-domain jitter measurements. Common misconceptions and definition e...
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This paper presents the physical, statistical, and mathematical background necessary for properly translating between frequency-domain phase noise and various time-domain jitter measurements. Common misconceptions and definition errors are exposed, as are methods for their correction, due to the different conventions in use for defining phase noise. Underlying limitations and assumptions involved in transforming between time-and frequency-domain noise descriptions are explained. Applications presented include: mapping between time and frequency noise specifications, creating statistically accurate jitter models, and properly interpreting phase noise and jitter measurements.
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